1. Field of the Invention
The present invention relates to an overflow detection circuit for a shifter.
2. Description of the Prior Art
When binary signals which denote positive or negative values are contained in the most significant bit of the data to be shifted, an overflow detection circuit is necessary to detect that the binary signals to the left by the shifter.
FIG. 1 shows a conventional overflow detection circuit. This figure shows a 4 bit shifter S comprising multiplexers 1, 2, 3, and 4. The shifter shifts inputs I.sub.0, I.sub.1, I.sub.2, and I.sub.3 by the bits specified by shift signals (S.sub.0, S.sub.1)=(0,0)(0,1)(1,0)(1,1). These shift signals are output as O.sub.0, O.sub.1, O.sub.2, and O.sub.3. The input I.sub.0 is connected to the input terminal (0) of the multiplexer 1 and the input terminal (2) of the multiplexer 2. The input 1 is connected to the input terminal (1) of the multiplexer 1, input terminal (0) of the multiplexer 2 and the input terminal (2) of multiplexer 3. The input I.sub.2 is connected to the input terminal (1) of the multiplexer 2, input terminal (0) of the multiplexer 3 and input terminal (2) of the multiplexer 4. Finally, input I.sub.3 is connected to the input terminal (1) of the multiplexer 3 and input terminals (0), (1) of the multiplexer 4. Further the input terminal (3) of each multiplexer 1, 2, 3, 4 and the input terminal (2) of the multiplexer 1 are set at ground. Multiplexers 1, 2, 3, and 4 select inputs to the input terminals (0), (1), (2), and (3) respectively corresponding to the shift signals (S.sub.1, S.sub.0)=(0,0), (0,1), (1,0), (1,1). These shift signals are used as outputs O.sub.0, O.sub.1, O.sub.2, O.sub.3. The coincidence detection circuit acts as an overflow detection circuit, uses the most significant bit 1 of the input data and the most significant bit O.sub.3 as inputs, detects coincidence and non-coincidence of these inputs, and outputs 0/1 according to coincidence/non-coincidence when "1" is output.
As is apparent from the conditions for selecting inputs according to the data inputs and shift signals (S.sub.1,S.sub.0) for the multiplexers 1, 2, 3, and 4, the case where (S.sub.1,S.sub.0)=(1,0) corresponds to one bit left shift. However, the coincidence detection circuit 5 compares the most significant bit I.sub.3 of the input data with the input I.sub.2 (=O.sub.3) shifted to the left by 1 bit. If the result is non-coincidence, the circuit overflows the input data.
In the overflow detection circuit of FIG. 1 the presence of overflow is detected each time the input is shifted by 1 bit. Therefore, 1 clock period must pass before the overflow is detected when multiple bits are shifted. This results in the operating speed of the circuit being slow.